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Straight from the zilog manual for add hl, <register>:QuoteCondition Bits Affected:S is not affectedZ is not affectedH is set if carry out of bit 11; reset otherwiseP/V is not affectedN is resetC is set if carry from bit 15; reset otherwiseTo be honest, I actually forgot that S and Z were ignored. I bet somewhere in one of my programs I did that wrong.
Condition Bits Affected:S is not affectedZ is not affectedH is set if carry out of bit 11; reset otherwiseP/V is not affectedN is resetC is set if carry from bit 15; reset otherwise
add c, a
ex bc, af add a, c ex bc, af
ld b, aBloop: inc c djnz Bloop dec c
add a, cLd c, a
My question is if this is the most efficient way for the solution.