Well, depending on how much backwards compatibility require, you could technically say that the advancement in processor design IS that process.

Heck, there's even an improved CPU called the ez80. Backwards compatible mode, but also its own instruction set, and it goes up into 50 MHz.

That's true too. Thanks to a faster opcode caller or something, right?

I believe on the ez80 instructions all generally fit into one t-state, or rather due to the way the ez80 is set up it can pipeline/decode instructions in advance and execute them within one t-state. On the z80, each cycle takes 3-6 t-states and i assume it's basically the same on the ez80. For example:
xor a takes one machine cycle of 4 t-states.
add a,3 takes two machine cycles, the first is 4 t-states and the second is 3, altogether 7 t-states.
add hl,de takes three machine cycles, the first two are 4 t-states and the third is 3, altogether 11 t-states.
add ix,de takes four machine cycles, three cycles of 4 t-states and the last one is 3, altogether 15 t-states.
ld (ix+4),a takes 5 M cycles, 4 t-states for the IX prefix, 4 more to read the opcode, 3 t-states to read the offset, 5 to add the offset and read a, 3 t-states to write a to the address.
rl (ix) takes six M cycles, amounting to 23 t-states. I'm not sure what each each cycle amounts to, i think first you've got the IX prefix (4 t-states), then the opcode (4 t-states), then the offset (here, +0, 3 t-states), i don't know what the others might be.

So i think on the ez80, these M cycles will be prefetched/decoded while the previous instruction/cycle decodes/executes (each instruction must be fetched, decoded, then executed) so that they can be immediately executed when the previous instruction ends.

EDIT: Also, i was just thinking about how convenient add hl,imm16 would've been. It'd save you from having to destroy bc/de.

I really like writing assembly for my hobby Z80 (actually, currently Z180) and have done that for a while; I have something like 40000 lines of ASM code in my system. And yes, I also have wondered what kind of added instructions would be most benficial, for ASM-coding and for compiler (another language I'm using is BASIC, and of course I have implemented a compiler for it).

So, here some of the instructions, which are appearing all the time in my existing code, or which I would consider usefull implemented as single byte opcodes (there are something like 7 to 11 single byte opcodes, which no-one or at least I am not using)

LD    rr,(HL)      where rr=BC, DE, HL
LD    (HL),ss     where ss=BC or DE
INC2  HL          same as INC HL two times
DEC2 HL

These are appearing so often, that in my assembler I have created pseudo-opcodes like LD DE,(HL)++  or LD HL,(HL).

For the compiler I would like to have following two single byte opcodes:

LD    DE,(nn)     where nn is 16 bit memory address
LD    HL,SP+s    i.e. HL gets the sum of SP and an 8-bit signed constanst; usefull not only for allocating/deallocating space from stack, but also building a reference to a variable in stack.

And what Z80 is really missing, is couple of indexing registers besides the IX and IY; so I would allocate two of the available single byte opcodes to prefixes for handling these new registers.

Another area where Z80 is lacking, is 16-bit operations. I really would like to have instructions like LD DE,(IX+n) implemented with just 3 bytes, instead of the current 6 bytes (I have also these pseudo-opcodes in my assembler, however, the saving in memory usage would really be wellcome). And yeah, there are a few other opcodes, which would be rather useful...

Hey Pekka, welcome to Omnimaga! You should head over and <a href=http://www.omnimaga.org/index.php?board=10.0>introduce yourself</a>.

Well, there's always the ability to treat any part of RAM like an accumulator register. That's very handy in the ez8.