« previous next »
Pages: 1 ... 33 34 [35] 36 37 ... 43   Go Down

Author Topic: Casio Prizm documentation  (Read 240137 times)

0 Members and 1 Guest are viewing this topic.

Offline SimonLothar

  • LV4 Regular (Next: 200)
  • ****
  • Posts: 129
  • Rating: +35/-1
    • View Profile
Re: Casio Prizm documentation
« Reply #510 on: April 07, 2011, 11:26:13 am »
The processor version register 0xFF000030 of the Prizm returns 0x10300B00.
According to the 7450/7451 hardware manual, appendix D, a CHIP-version code "is always "H'10" in the SH-4A".
The major version byte (VER) is 0x30.
The minor version byte (CUT) is 0x0B.
The product version register 0xFF000044 of the Prizm returns 0x00002C00.
Hence the Prizm processor seems to be a member of the SH-4A family, at least basically.
Another interesting thing is, that the major version byte is higher than on a 7780,
which major version byte is 0x20, according to the manuals.
Logged
I'll be back.

Offline fxdev

  • LV4 Regular (Next: 200)
  • ****
  • Posts: 177
  • Rating: +34/-6
    • View Profile
Re: Casio Prizm documentation
« Reply #511 on: April 07, 2011, 01:48:24 pm »
Wow, this is awesome!

Quote
IDA Pro 6.0 feature list
...
+ SuperH: added SH-4a instructions
...
So you need IDA 6.0 to fully disassemble the OS?
Unfortunately, the last cracked version seems to be 5.5 :(
Logged

Offline AngelFish

  • Is this my custom title?
  • Administrator
  • LV12 Extreme Poster (Next: 5000)
  • ************
  • Posts: 3242
  • Rating: +270/-27
  • I'm a Fishbot
    • View Profile
Re: Casio Prizm documentation
« Reply #512 on: April 07, 2011, 01:59:22 pm »
How could the processor have a SuperH 4A core? That would imply that the CPU is capable of several hundred MHz.
Logged
∂²Ψ    -(2m(V(x)-E)Ψ
---  = -------------
∂x²        ℏ²Ψ

Offline z80man

  • Casio Traitor
  • LV8 Addict (Next: 1000)
  • ********
  • Posts: 977
  • Rating: +85/-3
    • View Profile
Re: Casio Prizm documentation
« Reply #513 on: April 07, 2011, 02:23:27 pm »
Not only would it have several hundred mHz, but also support fpu and 3d graphic instructions.
Logged

List of stuff I need to do before September:
1. Finish the Emulator of the Casio Prizm (in active development)
2. Finish the the SH3 asm IDE/assembler/linker program (in active development)
3. Create a partial Java virtual machine  for the Prizm (not started)
4. Create Axe for the Prizm with an Axe legacy mode (in planning phase)
5. Develop a large set of C and asm libraries for the Prizm (some progress)
6. Create an emulator of the 83+ for the Prizm (not started)
7. Create a well polished game that showcases the ability of the Casio Prizm (not started)

Offline SimonLothar

  • LV4 Regular (Next: 200)
  • ****
  • Posts: 129
  • Rating: +35/-1
    • View Profile
Re: Casio Prizm documentation
« Reply #514 on: April 08, 2011, 04:17:01 am »
Quote from: SimonLothar on February 16, 2011, 02:05:49 pm
Another hint for expanded customization is the presence of at least two new processor instructions 0x00AB and 0x0nE3 (n=register-no.), which are not documented.
0x00AB and 0x0nE3 are new indeed, but not customized. Since the Prizm processor revealed, that it is a member of the SH-4A family, I had a closer look at the 7780 manual.
0x00AB is SYNCO (new with the 7780)
0x0nE3 is ICBI @Rn (new with the 7780)

BTW.: the SH-4A members are specified to run between 160 MHz and 600 MHz, depending on the processor type.
The SH-4 members are specified to run up to 240 MHz.
The SH-3 members are specified to run up to 200 MHz.
(http://www.renesas.eu/products/mpumcu/superh/superh_landing.jsp)
« Last Edit: April 08, 2011, 04:20:43 am by SimonLothar »
Logged
I'll be back.

Offline z80man

  • Casio Traitor
  • LV8 Addict (Next: 1000)
  • ********
  • Posts: 977
  • Rating: +85/-3
    • View Profile
Re: Casio Prizm documentation
« Reply #515 on: April 08, 2011, 04:26:48 am »
So why would Casio need to clear the pipeline with synco and invalidate the cache block with ICBI. Where do they use these commands.
Logged

List of stuff I need to do before September:
1. Finish the Emulator of the Casio Prizm (in active development)
2. Finish the the SH3 asm IDE/assembler/linker program (in active development)
3. Create a partial Java virtual machine  for the Prizm (not started)
4. Create Axe for the Prizm with an Axe legacy mode (in planning phase)
5. Develop a large set of C and asm libraries for the Prizm (some progress)
6. Create an emulator of the 83+ for the Prizm (not started)
7. Create a well polished game that showcases the ability of the Casio Prizm (not started)

Offline SimonLothar

  • LV4 Regular (Next: 200)
  • ****
  • Posts: 129
  • Rating: +35/-1
    • View Profile
Re: Casio Prizm documentation
« Reply #516 on: April 08, 2011, 04:43:16 am »
Quote from: z80man on April 08, 2011, 04:26:48 am
So why would Casio need to clear the pipeline with synco and invalidate the cache block with ICBI. Where do they use these commands.
According to the 7780 manual, p.68, SYNCO "Prevents the next instruction from being issued until instructions issued before this instruction have been completed". It is used every time the LCD-registers are accessed.
ICBI is used in the boot code several times. The corresponding register always loaded with 0xA0000000. If I remember well, it occurs a few times inside of the OS as well.
Logged
I'll be back.

Offline fxdev

  • LV4 Regular (Next: 200)
  • ****
  • Posts: 177
  • Rating: +34/-6
    • View Profile
Re: Casio Prizm documentation
« Reply #517 on: April 08, 2011, 12:44:19 pm »
Well, at least Insight can be compiled with -cpu=sh4 and -fpu=single
But I did not notice any difference.
Logged

Offline SimonLothar

  • LV4 Regular (Next: 200)
  • ****
  • Posts: 129
  • Rating: +35/-1
    • View Profile
Re: Casio Prizm documentation
« Reply #518 on: April 08, 2011, 02:03:36 pm »
Quote from: cfxm on April 08, 2011, 12:44:19 pm
Well, at least Insight can be compiled with -cpu=sh4 and -fpu=single
But I did not notice any difference.
Smart idea.
There will be differences, if you declare float-variables. The compiler uses fpu-commands, indeed. But, alas, the Prizm crashs with "Illegal Code Err", t. i. no fpu-support in the processor.
Logged
I'll be back.

Offline z80man

  • Casio Traitor
  • LV8 Addict (Next: 1000)
  • ********
  • Posts: 977
  • Rating: +85/-3
    • View Profile
Re: Casio Prizm documentation
« Reply #519 on: April 08, 2011, 02:19:24 pm »
This to me looks like Casio used a modified SH3. TI did the same thing with the z80 when they created the 83+. I would say the instruction set is the same as the SH3 with the added SYNCO and ICBI. I would also check into the commands related to ICBI as those may be included also. For the overall proc standard peripherals may or may not be included. For example I'm not sure if the peripherals for controlling cell phone communications are available. Addresses and the functionality of hardware may have been decided by Casio, so you can't rely on the addresses provided by Renesas for any of their procs.
Logged

List of stuff I need to do before September:
1. Finish the Emulator of the Casio Prizm (in active development)
2. Finish the the SH3 asm IDE/assembler/linker program (in active development)
3. Create a partial Java virtual machine  for the Prizm (not started)
4. Create Axe for the Prizm with an Axe legacy mode (in planning phase)
5. Develop a large set of C and asm libraries for the Prizm (some progress)
6. Create an emulator of the 83+ for the Prizm (not started)
7. Create a well polished game that showcases the ability of the Casio Prizm (not started)

Offline SimonLothar

  • LV4 Regular (Next: 200)
  • ****
  • Posts: 129
  • Rating: +35/-1
    • View Profile
Re: Casio Prizm documentation
« Reply #520 on: April 09, 2011, 04:22:53 am »
Quote from: z80man on April 08, 2011, 04:26:48 am
So why would Casio need ... synco and ... ICBI.
Because the Prizm processor is SH-4A-based (of course heavily customized). I do not think, that the processor is able to lie, when it says "I am a member of the SH-4A family", which it does, when you read the PVR.
Logged
I'll be back.

Offline fxdev

  • LV4 Regular (Next: 200)
  • ****
  • Posts: 177
  • Rating: +34/-6
    • View Profile
Re: Casio Prizm documentation
« Reply #521 on: April 14, 2011, 06:40:23 pm »
BIOS checksum (0x1FFFC):
0x00..0x02FF + 0x0340..0x01FFBF

OS checksum (0xB5FFF8):
0x020000..0xB5FEAF + 0xB5FEF0..0xB5FFF7
« Last Edit: April 14, 2011, 06:46:47 pm by cfxm »
Logged

Offline JosJuice

  • LV10 31337 u53r (Next: 2000)
  • **********
  • Posts: 1344
  • Rating: +66/-14
    • View Profile
Re: Casio Prizm documentation
« Reply #522 on: April 16, 2011, 06:28:11 am »
Quote from: cfxm on April 14, 2011, 06:40:23 pm
BIOS checksum (0x1FFFC):
0x00..0x02FF + 0x0340..0x01FFBF

OS checksum (0xB5FFF8):
0x020000..0xB5FEAF + 0xB5FEF0..0xB5FFF7

Are you talking about the memory locations of those checksums, or the checksums themselves? If it's the latter, which OS?
Logged

Offline fxdev

  • LV4 Regular (Next: 200)
  • ****
  • Posts: 177
  • Rating: +34/-6
    • View Profile
Re: Casio Prizm documentation
« Reply #523 on: April 16, 2011, 07:14:13 am »
Quote from: JosJuice on April 16, 2011, 06:28:11 am
Are you talking about the memory locations of those checksums, or the checksums themselves?

xyz checksum (0x??): <= Where the checksum is stored (4 bytes)
0x??..0x?? + 0x??..0x?? <= How it is calculated (simple sum)
« Last Edit: April 16, 2011, 07:16:28 am by cfxm »
Logged

Offline JosJuice

  • LV10 31337 u53r (Next: 2000)
  • **********
  • Posts: 1344
  • Rating: +66/-14
    • View Profile
Re: Casio Prizm documentation
« Reply #524 on: April 16, 2011, 08:52:24 am »
Ah, okay. Thanks for telling us.
Logged
Pages: 1 ... 33 34 [35] 36 37 ... 43   Go Up
« previous next »