Attached is a simple multi-cycle data path used in one of my classes.
One image shows the data path without pipelining, the other with.
The LC-2K is an 8-register, 32-bit computer. All addresses are
word-addresses. The LC-2K has 65536 words of memory. By assembly-language
convention, register 0 will always contain 0 (i.e. the machine will not enforce
this, but no assembly-language program should ever change register 0 from its
initial value of 0).
There are 4 instruction formats (bit 0 is the least-significant bit). Bits
31-25 are unused for all instructions, and should always be 0.
R-type instructions (add, nand):
bits 24-22: opcode
bits 21-19: reg A
bits 18-16: reg B
bits 15-3: unused (should all be 0)
bits 2-0: destReg
I-type instructions (lw, sw, beq):
bits 24-22: opcode
bits 21-19: reg A
bits 18-16: reg B
bits 15-0: offsetField (a 16-bit, 2's complement number with a range of
-32768 to 32767)
J-type instructions (jalr):
bits 24-22: opcode
bits 21-19: reg A
bits 18-16: reg B
bits 15-0: unused (should all be 0)
O-type instructions (halt, noop):
bits 24-22: opcode
bits 21-0: unused (should all be 0)
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Table 1: Description of Machine Instructions
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Assembly language Opcode in binary Action
name for instruction (bits 24, 23, 22)
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add (R-type format) 000 Add contents of regA with
contents of regB, store
results in destReg.
nand (R-type format) 001 Nand contents of regA with
contents of regB, store
results in destReg. This is
a bitwise nand; each bit is
treated independently.
lw (I-type format) 010 Load regB from memory. Memory
address is formed by adding
offsetField with the contents
of regA.
sw (I-type format) 011 Store regB into memory. Memory
address is formed by adding
offsetField with the contents
of regA.
beq (I-type format) 100 If the contents of regA
and regB are the same,
then branch to the address
PC+1+offsetField,
where PC is the address
of the beq instruction.
jalr (J-type format) 101 First store PC+1 into regB,
where PC is the address of the
jalr instruction. Then branch
to the address now contained in
regA. Note that this implies
if regA is the same as regB,
the processor will first store
PC+1 into that register, then
end up branching to PC+1.
In other words, FIRST the value
of PC+1 gets stored into regB,
then SECOND, the execution
jumps to the address in regA.
That means that if the two
registers specified are the
same, then it will first put
PC+1 into the register, and
then jump to the value in that
register. The net effect will
be jumping to PC+1.
halt (O-type format) 110 Increment the PC (as with all
instructions), then halt the
machine (let the simulator
notice that the machine
halted).
noop (O-type format) 111 Do nothing.
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If anyone wants to actually create something, this a good example to start with.
