Show Posts

This section allows you to view all posts made by this member. Note that you can only see posts made in areas you currently have access to.


Messages - the_mad_joob

Pages: 1 ... 6 7 [8] 9 10 ... 24
106
ASM / Re: 8X+ > flash writing question
« on: July 03, 2014, 09:44:57 pm »
I took a look at the datasheet, to understand things better.
Also, while i was thinking of a way to optimize the code, i found something worth mentionning (still in the wikiti code example).
First, let me put it there again :
Code: [Select]
   ld a,b
   xor (hl)
   bit 7,a
   jr z,programdone
   bit 5,(hl) !!!
   jr z,programwaitloop
As you can see, the code actually does 2 separate readings (XOR (HL) & BIT 5,(HL)).
The thing is, that if the chip happens to switch from "status" to "data" mode right before the second reading, bit 5 of actual data will be tested, potentially leading to an unwanted abort instruction.
To avoid that, i guess there is no other choice but to read only once, save the reading into a register, to be sure that you read bits 7 & 5 from the same byte.
Am i right about that potential breach ?

#####

As i said earlier, i decided to optimize the code in favor of fast & successful writings.
Here is what i intend to use :
Code: [Select]
;b = byte
;de = address

   ld hl,$0AAA
   ld (hl),l

   ld hl,$0555
   ld (hl),l

   ld a,$A0
   ld ($0AAA),a

   ld a,b
   ld (de),a

read

   ld a,(de)

   cp b ; yep, cp the fastest option for fast & successful writings (using xor directly would add 4 cycles for the backup)
   ret z

   ld c,a ; backup, to be sure to read bit 5 of the same byte later

   xor b
   ret p

   bit 5,c
   jp z,read

   ld a,$F0
   ld ($0000),a

   scf

   ret

;cf = 0 (success) | 1 (failure)
Thx in advance for letting me know if something is wrong or if you think it could be optimized more...

107
ASM / Re: 8X+ > flash writing question
« on: July 02, 2014, 12:06:11 pm »
Yo Streety =]
Something between an OS and a shell...

108
ASM / Re: 8X+ > flash writing question
« on: July 02, 2014, 01:43:24 am »
Oh, of course...
Thx chickendude =]

109
ASM / Re: 8X+ > flash writing question
« on: July 01, 2014, 11:31:25 am »
Thx a lot for all that in-depth infos DrD =]
Just a question, what you mean by "the code is no longer relocatable" ?

Also, i have another question now.
I was thinking of optimizing the 4 bus cycles part, using registers as much as possible.
As a result, the commands may be sent faster, maybe too fast.
Is a delay needed between the unlocks, write command, and data sending ?

110
ASM / Re: 8X+ > flash writing question
« on: June 29, 2014, 12:57:23 am »
Hmm, i find that "rest of the data is not guarenteed to be correct" pretty scary.
Looks to me like when the chip changes the read byte from "status" to "data", it doesn't update the bits all at once (theory).
Then, checking all the bits would be even more safe...

Thx for the data about timeout, too.
Maybe batteries becoming low in the middle of a writing procedure could also cause a timeout (another theory)...

111
ASM / Re: 8X+ > flash writing question
« on: June 28, 2014, 11:39:10 pm »
I think the "trick" here is that bit 7 will always be the opposite of the byte you're trying to write (here in b), so if bit 7 of b is 1, bit 7 of (hl) will be 0 (so XORing the two will always give you 1). If it's finished, then you'll get the same bit that's in b, so XORing them will give you 0 (so z will be set). I don't really know how all of it works, that's just what i got from calc84's message.

EDIT: And (hl) doesn't really return the value of (hl) but rather a status byte, so i think you could read from anywhere in flash (like "ld a,($4000) \ xor b") and it would return the same thing until the thing finishes. Also, if you just cp (hl) there's a chance that the status byte has the same value as the byte you're trying to write.
That is how i understood it, too.
2 cases :
1) writing complete, reading will return the effective byte at the address, therefore all bits will match between the write & the read.
2) writing incomplete, reading will return a status byte which bit 7 is the opposite of bit 7 of the byte you asked to write (ugly sentence, i know XD).
The thing is, that if bit 7 of the status byte is "guaranteed" to be the opposite, then i don't see how there is a chance to have a match when comparing the 2 bytes.
I mean, comparing byte %1XXXXXXX and byte %0XXXXXXX can never set the zero flag, so why wasting some cycles with that slow BIT instruction ?

Sorry again to bother you with that guyz, but that's important, cause such code can be iterated a lot when writing to flash and highly deserves to be speed-optimized.

112
ASM / Re: 8X+ > flash writing question
« on: June 28, 2014, 06:28:19 pm »
While a flash write is in progress, when you read a byte from flash, you get a status byte rather than actual data. Bit 7 is guaranteed to be the opposite of the data being written, and conversely, when it succeeds, bit 7 is guaranteed to match the data that was written. Bit 5 of the status byte gets set when there is an error, which can be either a timeout or trying to write a 1 over a 0. Bit 5 should be checked only when you already know bit 7 doesn't match, of course.
Fat thx for the explanation =]
Anyway, whether reading returns a status byte or the actual data, i still think a simple LD A,(HL) \ CP B or LD A,B \ CP (HL) would be more appropriate (faster & lighter).
Am i wrong ?
Also, other question : What can cause a timeout ?
Thx again for your time...

113
ASM / Re: 8X+ > flash writing question
« on: June 28, 2014, 12:03:48 pm »
No, haven't tried yet any attempt to write.
You know, that's the kind of thing you want to understand before trying on real hardware =P
I don't really believe it, but i could potentially imagine that the flash chip behaves differently when he hasn't totally finished accepting a write attempt (depending on the used op code).

114
ASM / 8X+ > flash writing question
« on: June 27, 2014, 12:39:06 am »
Welcome...

Alright, i'm about to code a few routines that will write to archive space.
Of course, i'm gonna have to follow what is written on that page : http://wikiti.brandonw.net/index.php?title=83Plus:OS:Raw_Flash_Commands
Still, there is a part of the code that i don't understand :
Code: [Select]
ld a,b
xor (hl)
bit 7,a
jr z,programdone
bit 5,(hl)
jr z,programwaitloop
Why using XOR (HL) and checking bit 7 of A where a CP (HL) would be faster ?
Also, i really have no idea what is the point of checking bit 5 of (HL).

Any clarification greatly appreciated =]

115
ASM / Re: port 1 stuff
« on: May 23, 2014, 02:35:11 pm »
Wow. Your research is making this hardware sound more and more obscure. O.O What the hell TI ?
This behavior is most likely due to capacitance in the keyboard traces. When you select a group for reading, charge almost instantly rushes onto the group traces on the PCB, so you can read instantly. But when you unselect a group, TI makes no effort to discharge the traces. (They're also too cheap to add a 1-cent diode to each key so that we could detect multiple key presses without ghosting.) The pins that control the group traces simply go into a high-impedance state, meaning change can't flow back into them. As a result, electric charge stays on the traces until internal resistance dissipates it. When you read from the keyboard right after disabling a group, the charge that was previously on the keyboard traces is still there, giving you the false signal. The capacitance effect is small and the charge dissipates in just a few microseconds, but the Z80 is running fast enough that we can see those microseconds.
Excellent, some hardware explanations =]
Makes me remember how far my knowledge of electronic suck XD

I still need at least a few testers (prgm available @ my previous post).
 

116
ASM / Re: port 1 stuff
« on: May 21, 2014, 08:14:48 am »
Allright, performed a few verifications, and nothing contradictory showed up.
I have reformated post#1 with all my discoveries.

Right now, i need a few testers (attached program).
You can use it on any 8X+, except the CSE.
Just run it with Asm(.
As soon as it starts, you have 3 seconds to hold the desired key(s).
Plz hold the keys until the program tells you to release them.
The returned values are for all available CPU speeds on your calc (in order : 0,1,2,3).
What it does is check the needed delay for the pressed key(s) to be disabled.
Despite it recognizes all possible key combinations, i'm particularly interested in the following ones :

1) Check all keys, separately, and let me know the maximum delays the program returns.
The "5" key is expected to have the highest delays, whereas "ALPHA" should have the lowest.

2) Check the following combinations :
LEFT + 3 2 1 STO TRACE
RIGHT - 6 5 4 LN ZOOM
UP * 9 8 7 LOG WINDOW

Thx in advance for your time =]

117
ASM / clean asm program exiting
« on: May 20, 2014, 06:49:14 am »
Hello =]

It's been a while since i wanted to find a way to exit an asm program, the "clean" way.
By "clean", i mean by restoring all the previous home entries properly, and eventually the graph screen (in case the program was executed in horiz mode), without any unwanted effects.
In other words, you get what you would have after executing a basic program, no matter what you've been displaying.
The challenge was to make it without using any custom ram locations, as well as stack entries.
Also, the code is compatible with all 8X+ models (CSE excluded), and all OS (mathcrap included).
Of course, i guess that is mainly useful for standalone programs (nostub).
It is optimized in favor of size.

Here is the magic formula :

HEADER

Code: [Select]
.db t2bytetok,tasmcmp
    bit 5,(iy+$44)
    jr nz,backup_over
    ld a,(currow)
    ld (textshadcur),a
backup_over
Your code starts here...

TAIL

Code: [Select]
...Your code ends here.
    bit 5,(iy+$44)
    jr nz,restore_mp
    ld a,(flags+sgrflags)
    rra
    jr nc,restore_home
    bcall(_grbufcpy)
restore_home
    bcall(_rstrshadow)
    ret
restore_mp
    ld a,3
    out (5),a
    ld b,64
    ld hl,$DA7E
    bcall(_restoredisp)
    xor a
    out (5),a
    ret

NOTES

If you intend to use _clrscrn, _clrscrnfull, or any large character displaying rom call, just add "res apptextsave,(iy+appflags)" after the header, as well as "set apptextsave,(iy+appflags)" before the tail.
Basically, if textshadow or cmdshadow are altered, the home screen won't be what it was before the program execution.
Same goes for plotsscreen for the graph screen.

118
ASM / Re: port 1 stuff
« on: May 20, 2014, 06:03:43 am »
Yeah, obscure as hell.
An important thing to note is that all my tests were realised checking the needed delay to disable keys while those are actually being pressed.
Due to how the keyboard works, i think it's impossible to test those delays without pressing them.
In other words, it won't be possible to know the real needed time for the keybord to disable unpressed keys.

119
ASM / Re: port 1 stuff
« on: May 20, 2014, 01:30:27 am »
Did some new tests.
I can say i was a bit surprised by the results.

Examples of some delays my program returns.
The values are the needed delay to disable those keys while being pressed, at 15 Mhz :

DOWN : 21
LEFT : 21
RIGHT : 22
UP : 20
DOWN+LEFT : 15
DOWN+LEFT+RIGHT : 13
DOWN+LEFT+RIGHT+UP : 12
As you can see, it appears that the more keys are being pressed in the same group, the faster it takes to disable them.

And now, some results in different groups :
LEFT+-+9+(+SIN+MATH+DEL : 24
LEFT+++3+2+1+STO+TRACE : 123
It took me a while to figure out why such a huge difference.
In the first case, all keys correspond to different key bits, and in the second, to the same.

120
ASM / Re: port 1 stuff
« on: May 17, 2014, 06:53:54 pm »
It requires a bit more investigations, but yeah, i do that for the community (and personal curiosity) and i hope it will be of use for some.
I'm currently coding some stuff at work for a few testers...

Pages: 1 ... 6 7 [8] 9 10 ... 24