Hello omnimaga, long time no see. I'm building an operating system for the TI-84+ series calculators(and perhaps the TI-83+SE if I can find someone to test it during the beta phase). Part of its design includes exploiting the hardware's error traps (eg. No-EXEC, Port elevation, authorized read, etc.), however, I can't find any info stating whether the traps simply reset the CPU or if they execute an NMI(eg. an RST 60h) . Does anyone have any info on this behavior? If so, please reply! Thanks!

Ok that is what I needed to know - no need to build an NMI trap at 60h if there is no way to trigger it . I am using WikiTI - it is the most complete documentation I can find on the Z80/EZ80 based calculators. I was aware of the NMI traps used by the 84+CE, but I'm also aware that even though the rom call interface is written in such a way that programs written for CISPL and QSPL would be cross-compatible to an extent, assembly programs would require some translation due to the physical 24-bit bus(in particular, non-relative jumps and anything involving register loads from memory would require modification)(Since the QSPL/CISPL interpreters run within a logical 16-bit stack environment, anything that directly adresses the stack would need to be rewritten to work within 24-bit. Also, integers would overflow at higher numerical values, so programs relying on this behavior may behave abnormally unless I find some way to mask the MSB while preserving the sign bit, but then you wont have the benefit of 24-bit integers . And all of that is without mentioning that any ASM programs contained within the script would require a rewrite.). For this reason and others(for example, the fact that you cannot practically build an OS for the TI-84+CE), I'm going to first focus on getting this OS running on the 128k monochrome calculators, then get the 48k calculators working(did I mention that the kernel memory allocation routines work within the full logical 24 bit environment provided by the ASIC? They will need to be rewritten slightly to deal with the discrepancy between those two revisions), then if I'm feeling particularly daring I might try to get this thing running on the TI-84+CSE.